1. Field of the Invention
The present invention generally relates to a thin film transistor (TFT) and the manufacturing method thereof. More particularly, the present invention generally relates to a thin film transistor (TFT) having a lightly doped amorphous silicon channel layer and the manufacturing method thereof.
2. Description of the Related Art
In recent years, a variety of macromedia electronic devices and products are drastically developed due to the rapid development of the semiconductor device and the user interface of the device. Conventionally, since the cathode ray tube (CRT) display device is low-cost and has high performance, it is widely used display device. However, as to the display device of the personal computer, the cathode ray tube (CRT) display has the disadvantages of large size and high power consumption. Accordingly, the liquid crystal display (LCD) being small, lightweight, use low operational voltage, low power consumption, radiation free and environmentally friendly, gradually replaced the conventional CRT display. In recent years, the liquid crystal display (LCD), for example, the thin film transistor (TFT) liquid crystal display (LCD) has become the main stream of the display devices.
In general, the conventional thin film transistor (TFT) may be classified into amorphous silicon thin film transistor (TFT) and polysilicon thin film transistor (TFT). It is noted that, the technology of low temperature polysilicon (LTPS) is different from the technology of conventional amorphous silicon (α-Si). In the low temperature polysilicon (LTPS) technology, the electron mobility can be enhanced to more than 200 cm2/V-sec. Therefore, the size of the thin film transistor (TFT) can be minimized, the aperture ratio of the display can be enhanced, and the power consumption can be reduced. However, because of the manufacturing process of the amorphous silicon thin film transistor (TFT) technology is well developed, simple and low-cost, the amorphous silicon thin film transistor (TFT) technology is still the main stream of the array of the display device.
FIG. 1 is a cross-sectional view schematically illustrating the structure of conventional amorphous silicon thin film transistor (TFT). Referring to FIG. 1, the thin film transistor (TFT) 100 includes a substrate 110, a gate 120, an inter-gate dielectric layer 130, a channel layer 140 and source/drain regions 150. The gate 120 is disposed on the substrate 110. The inter-gate dielectric layer 130 is disposed on the substrate and covers the gate 120. The channel layer 140 is disposed on a portion of the inter-gate dielectric layer 130 that at least covers the gate 120. The source/drain regions 150 are disposed on the channel layer 140 and are separated by a distance. When the gate 120 operates to supply an operating voltage to the channel layer 140, the source/drain regions 150 are electrically connected by the channel layer 140.
The manufacturing method of the channel layer 140 of the conventional thin film transistor (TFT) 100 includes the following steps. First, the substrate 110 is transported into a reaction chamber (not shown) and the substrate is subjected to a reaction gas mixture comprising of silane (SiH4) and hydrogen (H2) in the reaction chamber to form an intrinsic amorphous silicon layer. Next, the amorphous silicon layer is patterned to form the channel layer 140.
Accordingly, because the channel layer of the thin film transistor (TFT) is an intrinsic amorphous silicon layer, the electron mobility and the turning-on-current are not high enough when the thin film transistor is operated.